Digital servo mechanism

ABSTRACT

A digital servo-mechanism for controlling a frequency controlled two-phase servo-motor is provided. Instruction pulses for moving the servo-motor, by rotating the same through an angle proportional to the number of the instruction pulses, are fed to the servo-mechanism. A position angle detector, such as a synchro-resolver, detects the rotation angle of the servo-motor and produces feedback pulses proportional to the rotated angle of the servo-motor. Any deviation between the instruction pulses and the feedback pulses is converted into sine and cosine waves whose frequency is proportional to the deviation. The servo-motor is controlled by the sine and cosine waves.

United States Patent Okuda et al.

[ June 26, 1973 1 DIGITAL SERVO-MECHANISM Assignee:

Tokyo Shibaura Electric Company,

Ltd., Kawasaki-shi, Japan Filed:

Sept. 16, 1971 Appl. No.: 181,172

Foreign Application Priority Data [56] References Cited UNITED STATESPATENTS 3,175,138 3/1965 Kilroy et al. 318/604 X 2,849,668 8/1958 Tripp318/605 X 3,523,231 8/1970 Arthur et al. 318/603 X Primqry Ex aminerBenjan1in Dobeck A ttorney-Norman F. Oblon, Marvin J. Spivak et al.

[57] ABSTRACT A digital servo-mechanism for controlling a frequencycontrolled two-phase servo-motor is provided. Instruc- Sept. 16, 1970Japan 45/80458 tion pulses for moving the servmmotor, by rotating theSept. 16, 1970 Japan 45/80459 Same through an angle proportional to thenumber of 1970 Japan 45/91972 the instruction pulses, are fed to theservo-mechanism. 1970 45/109713 A position angle detector, such as asynchro-resolver, Dec. 11, 1970 Japan 45/109715 detects the rotationange of the servmmotor and p duces feedback pulses proportional to therotated angle Cl 318/603 318/606 318/601 of the servo-motor. Anydeviation between the instruc- 318/599 tion pulses and the feedbackpulses is converted into Int. Cl. G051) 19/28 Sine and cosine waveswhose frequency is proportional Field of Search 318/603, 606, 600, tothe deviation The servoqnotor is controlled by the 318/601 599 sine andcosine waves.

7 Claims, 15 Drawing Figures {I4 {/3 {/5 [I6 PULSE 7 GATE PULSE FUNCTIONGENERATOR CIRCUIT COUNTER GENERATOR l8, POWER l AMPLIFIER I8 17 2 I9 19FRE UENCY DEVIATION MuLgpuER POSITION INSTRUCTION REGISTER DETECTORPULSES FEEDBACK PULSES I p PATENTEDJUNZB 1975 3. 742.326

SHEET-1 0F 8 {I4 {/3 {l5 PULSE Y GATE PULSE FUNCTION GENERATOR CIRCUITCOUNTER GENERATOR POWER AMPLIFIER [8 J I7 I82 I9 {20 [/9 I! v- DEVIATIONPOSITION INSTRUCTION REGISTER DETECTOR PULSES 2/ FEEDBACK PULSES 2 P5.P8. PULSEGEN. L11111111111111111111111111 FREQ.DI\I.(I6I) 1 1 1 1 1 1 11 1 1 1 1 1 FREQ. DIV. (I62) 1 1 1 1 1 1 FREQ.D1v.(|s3) 1 1 1FREQ.D1\/.(164) 1 INVENTORS- NOBUO OKUDA BY 0, I

MASAHIKO SEKIGUCHI PATENTEUJUKZB 197s SHEEI 6 0f 8 FIGS FLIP F|.0P(405)FLIP FLOP (406) b) ANALOG GATE(6I5) 0 mm mm c) GATEINPUTM) a) GATE INPUT(443) O. m m m m w a A G H m m m H A H R N M M A A A I \U n FATENTEB Jul2 6 I973 SHEEI 6 0F 8 PAIENTEU JUII 26 I873 SHEET 7 UF 8 CONTENT OFREVERSIBLE COUNTER L IllllIIlll 65432 Illl REFERENCE PULSE I I l CLOCKPULSE I ZERO SIGNAL (806) E FLIP FLOP (807) I 1 I OR PWM SIGNAL FLIPFLOP (808) OR CORRECTION PULSE FIG.9

TRANSISTOR I820) TRANSISTOR I 82I I TRANSISTOR AND GATE (8I4) FIG. I5

PATENTEUJUHZS I973 SHEET 8 []F 8 FIG. IO

SINE WAVE H HHHHHHH H HHHHHHH TRANSISTOR (820) HUHUUUUH TRANSISTOR (82!)FIG. l2

FIG. I?

DIGITAL SERVO-MECHANISM BACKGROUND OF THE INVENTION 1. Field of theInvention This invention relates generally to a digital servomechanism,and more particularly to a digital servomechanism in which theservo-motor thereof is controlled by sine and cosine waves, thefrequency of which is variable and which is generated by a digitalcircuit.

2. Description of the Prior Art In the past, it has been well known touse a two-phase servo-motor in a servo-mechanism system. The twophaseservo-motor has an excitation winding and a control winding, and isoperated by flowing a first alternating current through the excitationwinding and simultaneously flowing a second alternating current,differing 90 in phase from the first alternating current, through thecontrol winding. It is also well known that there are two methods forcontrolling the speed of the servomotor. One method is voltage control,and the other is frequency control.

The voltage control method of controlling the speed of the servo-motoris done by flowing an alternating current of a constant voltage and of aconstant frequency through an excitation winding, and flowing analternating current of the same frequency and of a variable voltagethrough the control winding. The speed of rotation of the servo-motor isthen controlled by varying the variable voltage being supplied to thecontrol winding. One problem in the voltage control method is that theconstant current always flows through the excitation winding even if theservo-motor does not rotate so that the efficiency thereof is very low.Furthermore, since the voltage supplied to the two windings are not thesame, an elliptic rotating magnetic field is induced, and harmonics arethereby generated.

In view of the foregoing, the frequency control method of controllingthe speed of the servo-motor has been found to be preferable. Oneproblem here, however, is that it is difficult to obtain a variablefrequency supply. Recently, with the wide usage of numerical controldevices for machine tools and the like, it has become even moredifficult to provide a variable frequency supply in that a digitaloperation is required.

SUMMARY OF THE INVENTION Accordingly, it is one object of the presentinvention to provide a new and improved unique digital servomechanism.

It is another object of the present invention to provide a new andimproved unique digital servomechanism in which a two-phase servo-motoris controlled by an alternating current having a variable frequency.

It is one other object of the present invention to provide a new andimproved unique digital servomechanism in which a variable frequencysupply is provided by a digital operation.

It is still another object of the present invention to provide a new andimproved unique digital servomechanism in which an alternating currenthaving a variable frequency is modulated into a PWM signal.

One further object of the present invention is to provide a new andimproved unique digital servomechanism in which the waveforms of thecurrent flowing through the windings of the servo-motor aresatisfactorily shaped.

Briefly, in accordance with the present invention, these and otherobjects are obtained, in one aspect, by providing a two-phaseservo-motor having an excitation and a control winding. A positiondetector is also provided for detecting the angular position of theservo-motor and for generating feedback pulses, the number of which isproportional to the angular position. Instruction pulses are fed to movethe servo-motor by an angle of rotation which is proportional to thenumber of the instruction pulses. A deviation register is also providedto count the feedback pulses and the instruction pulses. A gate circuitis provided to multiply the contents of the deviation register withreference pulses generated by a pulse generator to thereby generate asuccessive pulse train. A pulse counter is provided to count thesuccessive pulse train and to convert the deviation into a frequencysignal. Sine and cosine waves are generated in accordance with thefrequency of a function generator. A power amplifier is provided foramplifying the sine and cosine waves to thereby drive the exciting andcontrol windings of the servo-motor.

BRIEF DESCRIPTION OF THE DRAWINGS A more complete appreciation of theinvention will be readily obtained as the same becomes better understoodby reference to the following detailed description when considered inconnection with the accompanying Drawings, wherein:

FIG. I is a block diagram of one preferred embodiment of a digitalservo-mechanism according to the present invention;

FIG. 2 is a logic diagram of a deviation register, a pulse generator anda gate circuit for a digital servomechanism according to the presentinvention;

FIG. 3 is a chart illustrating the pulse sequence provided by the pulsegenerator and the gate circuit of the digital servo-mechanism accordingto the present invention;

FIG. 4 is a logic diagram of a pulse counter of a digitalservo-mechanism according to the present invention;

FIG. 5 is a time chart to explain the pulse counter;

FIG. 6 is a block diagram of a function generator and a power amplifierof one preferred embodiment of a digital servo-mechanism according tothis invention;

FIG. 7 is a time chart to explain the function generator;

FIG. 8 is a block diagram of another preferred embodiment of a digitalservo-mechanism according to this invention;

FIGS. 9 through 13 are time charts to explain the embodiment shown inFIG. 8;

FIG. 14 is a block diagram of still one other preferred embodiment of adigital servo-mechanism according to this invention; and,

FIG. 15 shows the frequency characteristics of the power amplifier ofFIG. 6.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to thedrawings wherein like reference numerals designate identical, orcorresponding parts throughout the several views, and more particularlyto FIG. 1 thereof wherein a digital servo-mechanism according to thepresent invention is shown as having instruction pulses 11 which are fedto a deviation register 12. The instruction pulses 11 are employed tomove a two-phase servo-motor 18 by rotating the same through an angleproportional to the number of the pulses 11. The angle of rotation ofthe servo-motor 18 is detected by a position detector 19, such as asynchro-resolver, which converts the angle of rotation into a train offeedback pulses 21, and then transmits the same to the deviationregister 12. The deviation register 12 is employed as a reversiblecounter, and counts up and down the instruction pulses 11 and thefeedback pulses 21 and registers the deviation between them. Thedeviation is then transmitted to a gate circuit 13.

A pulse generator 14 is provided, and transmits a train of referencepulses to the gate circuit 13. The gate circuit 13 multiplies thereference pulses with the deviation output of the deviation register 12and thereby converts the deviation into a successive pulse train, thenumber of pulses of which is proportional to the deviation.

The successive pulse train so generated is then fed to a pulse counter15. The pulse counter 15 counts up the pulses from 0 to a certain numberat which time an output pulse is emitted and then counts down to 0 atwhich time another output pulse is emitted. The frequency of the outputpulses of the pulse counter 15 is thereby proportional to the content ofthe deviation register 12. The feedback pulses 21 are fed to the pulsecounter 15 through a frequency multiplier 20 to thereby provide a speedfeedback loop. The output of the pulse counter 15 is fed to a functiongenerator 16.

The function generator 16 generates a sine wave and a cosine waveaccording to the frequency defined by the pulse counter 15, and the sineand the cosine waves are then amplified by a power amplifier 17. Theoutputs of the power amplifier 17 are then fed to an exciting winding 18and a control winding 18 to thereby control the speed of the servo-motorl8.

It should be understood that if the instruction pulses 11 have a plussign and are to rotate the servo-motor 18 in the forward direction, thenthe instruction pulses 11 will be counted up by the deviation register12 to thereby cause the servo-motor 18 to rotate in the forwarddirection. The position detector 19 will detect the rotation of theservo-motor 18 and will transmit feedback pulses 21 which have a minussign. The deviation register 12 will subtract the feedback pulses 21from its content, and when the same becomes 0, the servomotor 18 willstop. In accordance with the above, it is apparent that the servo-motor18 can rotate by an angle of rotation designated by the instructionpulses 11. If the servo-motor 18 were to rotate in the reversedirection, the instruction pulses 11 would have a minus sign, and thefeedback pulses 21 would then have a plus sign.

The details of each portion of the embodiment set forth in FIG. 1 willbe described hereinafter.

FIG. 2 shows a logic diagram of the deviation register 12, the gatecircuit 13, and the pulse generator 14. In this embodiment, thedeviation register 12 contains five flip-flops 121 through 125 tothereby constitute a binary counter. Ifthe content of each of theflip-flops 121 through 125 is 0, then the output Q of each of theflipflops will be 0 and the output 6 will be 1, and if the content is l,the output Q will be I and the output Q will be 0. The flip-flops 121through 124 are utilized to designate the magnitude of the deviation,and the flipflop is utilized to designate the sign of the deviation. Theoutputs Q of each of the flip-flops 121 through 124 are fed to AND gatesthrough 133, respectively. The outputs Q of each of the flip-flops 121through 124 are fed to AND gates 138 through 141, respectively. OR gates134 through 137 are provided, and are fed input pulses from the ANDgates 130 and 138, the AND gates 132 and 140, and the AND gates 133 and141, respectively. The output pulses of each of the OR gates 134 through137 are fed to the flip-flops 122 through 125, respectively.

The instruction pulses 11 are fed to the OR gate 135. Each one of theinstruction pulses 11 is employed to move the servo-motor 18 by a givenangle of rotation, such as 3. The feedback pulses 21 are fed to theflipflop 121. The feed back pulses 21 are transmitted from the positiondetector 19 when the servo-motor 18 moves 3/4 of the angle of rotation.In addition, there are provided plus sign pulses 128 and minus signpulses 129. The plus sign pulses 128 are fed to the AND gates 130through 133, and the minus sign pulses 129 are fed to the AND gates 138through 141.

The flip-flop 121 alternatively changes its state from O to 1 or from Ito 0 in response to the arriving of the feedback pulses 21. Theflip-flop 122 also alternatively changes its state when the output Q ofthe flip-flop 121 changes from 1 to 0 in the presence of a plus signsignal 128, or when the output 6 changes from 1 to 0 in the presence ofa minus sign signal 129. The other flip-flops 123 through 125 operate inthe same manner as the flip-flop 122. The flip-flop 123, however, willalso change its state in response to the presence of the instructionpulses 11.

The outputs Q of each of the flip-flops 121 through 124 are also fed toAND gates 144 through 147, respectively. The outputs Q of each of theflip-flops 121 through 124 are also fed to AND gates 148 through 151,respectively. The output 6 of the flip-flop 125 is simultaneously fed tothe AND gates 148 through 151. The output Q of the flip-flop 125 issimultaneously fed to the AND gates 144 through 147. The outputs of theAND gates 144 and 148 are fed to an OR gate 152. The outputs of the ANDgates and 149 are fed to an OR gate 153. The outputs of the AND gates146 and 150 are fed to an OR gate 154. The outputs of the AND gates 147and 151 are fed to an OR gate 155. The outputs of the OR gates 152through 155 are hereinafter referred to as the content of the deviationregister 12.

As described before, the flip-flop 125 serves to designate the sign ofthe deviation, and if the output 6 thereof is I, it serves to designatea plus sign, and if the output Q thereof is I, it serves to designate aminus sign. Now, it should be understood that when the output Q of theflip-flop is 1, the AND gates 148 through 151 will open and the contentof the deviation register 12 will be designated by the outputs Q of t heflip-flops 121 through 124 and that when the output Q of the flipflop125 is l, the AND gates 144 through 147 will open and the content of thedeviation register 12 will be designated by the output Q of theflip-flops 121 through 124. The relationship between the content of thedeviation register 12 and the flip-flops 121 through 125 is shown inTable I.

TABLE 1 The content of Flipthe deviation Flop Flop Flop Flop 125register 121 I22 123 124 the sign +1 5 1 I l l +1 4 0 l l l 0 +3 1 i i)o 6 +2 0 l 0 0 0 +1 1 0 0 0 0 l 0 l l l 1 2 l 0 l l l 3 0 0 l l 1 i 5 bb b o i In the above Table 1, it is seen that in the describedembodiment a maximum count over or below -1 5 cannot be provided.Obviously, it can be easily understood that this problem can be avoidedby providing more flip-flops. Furthermore, in the deviation register 12shown in FIG. 2, when the content of the deviation register 12 is 00000and the feedback pulses 21 and the minus sign signal 129 arrive, theflip-flops will change to 1 1 l l l, and thus unpreferably the contentof the deviation register 12 will still be 0. Accordingly, if thecontent of the flip-flop 125 changes from 1 to 0, the deviation register12 must subtract a 1 from its content so as to become 01111 or 1.

In the above construction of the deviation register 12, the operation isas follows.

As beforementioned, the instruction pulses 21 are employed to move theservo-motor 18, and if it is desired to move the servo-motor 18 in theforward direction, the plus sign pulses 128 are also fed with theinstruction pulses 11. The binary counter will then count up theinstruction pulses 11 so that the servo-motor 18 will rotate in aforward direction according to the deviation. The position detector 19will then detect the angular position of the servomotor l8 and transmitcorresponding feedback pulses 21 with a minus sign pulse 129 in order toenable a subtraction from the content of the flip-flop binary counter.When the content of the binary counter or the deviation register 12becomes 0, the servo-motor 18 will stop. Now, if it is desired to movethe servo-motor 18 in a reverse direction, the instruction pulses 11with minus sign pulses 129 are fed. The binary counter will then countdown the instruction pulses 11, so that the servo-motor 18 will rotatein a reverse direction according to the deviation. The position detector19 will then detect the angular position of the servo-motor 18 andtransmit the corresponding feedback pulses 21 with a plus sign pulse 128to enable an addition to the content of the flip-flop binary counter.When the content of the binary counter or the deviation register 12becomes 0, the servo-motor 18 will stop.

Referring now to FIG. 3, a chart illustrating the pulse sequence forexplaining the pulse generator 14 and the gate circuit 13 of FIG. 2 istherein set forth. The pulse generator 14 generates a reference pulsetrain as shown in FIG. 3. Every 16th pulse, a synchronizing pulse isemployed. The reference pulse train is then serially fed to frequencydividers, such as flip-flops 161 through 164, and is divided as shown inFIG. 3. The outputs of each of the frequency dividers 161 through 164are fed to AND gates 156 through 159, respectively. The other input tothe AND gates 156 through 159 are fed from the OR gates 152 through 155,respectively. The output pulses of the AND gates 156 through 159 are fedthrough an OR gate 169 to AND gates 170 and 171. The other input to theAND gates 170 and 171 are the outputs O and Q of the flip-flop 125,respectively. An output of the AND gate 170, which hereinafter will bereferred to as the add command pulse 173, is fed to the pulse counter15, and also to an OR gate 172. An output of the AND gate 171, whichhereinafter will be referred to as the subtract command pulse 174, isfed to the pulse counter 15, and also to the OR gate 172.

As described before, the outputs of OR gates 152 through 155 designatethe content of the deviation register 12 in binary code, and each outputcorresponds to the decimal code number 1,2,4 and 8. The frequencydividers 164 through 161 feed 1,2,4 and 8 pulses, respectively, to ANDgates 156 through 159 in each time cycle of the pulse generator 14. Thenumber of output pulses of the OR gate 169 within each cycle time istherefore equal to the content of the deviation register 12. In FIG. 3,the case is shown, by example, wherein the content of the deviationregister 12 is 1010 in binary code or 10 in decimal code. Accordingly,as the pulse generator 14 serially generates the reference pulses, theoutput pulses of the OR gate 169 will become a successive pulse trainand the number of which arrive within a certain time range is nearlyproportional to the content of the deviation register 12 even if thecontent therein is varied.

Also, if the content of the deviation register 12 has a plus sign, thenthe AND gate 170 will open and add command pulses 173 are fed to thepulse counter 15 with the successive pulse train 175. If the content ofthe deviation register 12 has a minus sign, then the AND gate 171 willopen and subtract command pulses 174 are fed to the pulse counter 15.

FIG. 4 is a block diagram of the pulse counter 15, and it is seen thatthe same closely resembles the deviation register 12 of FIG. 2.Flip-flops 401 through 405 correspond to the flip-flops 121 through 125.AND gates 407 through 410 and 412 through 415 correspond to the ANDgates 130 through 133 and 138 through 141, and OR gates 417 through 420correspond to the OR gates 134 through 137. The feedback pulses 21, theplus sign pulses 128, the minus sign pulses 129 and the instructionpulses 11 in FIG. 2 correspond to the successive pulse train 172, theadd command pulses 173, the subtract command pulses 174 and the feedbackpulses 21 in FIG. 4, respectively. Furthermore, AND gates 422 through429 correspond to the AND gates 144 through 151, and OR gates 430through 433 correspond to the OR gates 152 through 155. The connectionof above elements in FIG. 4 is the same as that of FIG. 2. Outputs 434through 437 of the OR gates 430 through 433 or the content of the pulsecounter 15 is fed to the function generator 16. The output Q of theflip-flop 405 is fed to AND gates 411 and 439, and the output 6 is fedto AND gates 416 and 438. The outputs of the AND gates 411 and 416 arefed to the flip-flop 406 through an OR gate 421. The output Q 443 of theflip-flop 406 is fed to the AND gate 439. The output 0 444 of theflip-flop 406 is fed to the AND gate 438. The outputs of the AND gates438 and 439 are fed to an OR gate 440, and the output 446 of the OR gate440 is fed to an inverter 441 which provides the output 445.

In FIG. 1, the feedback pulses 21 were fed to the pulse counter 15through the frequency multiplier 20, while in FIG. 4, the feedbackpulses 21 are fed to the flipflop 403, such that the feedback pulses 21are multiplied four times as compared to the successive pulse train 172.As such, the frequency multiplier 20 is not provided here because thefeedback pulse 21 is substantially multiplied four times by feeding thefeedback pulse 21 to the third stage of the counter 15. Of course it canbe easily understood that the same effect can be obtained by providingthe frequency multiplier 20 to multiply the feedback pulse 21 four timesand then feeding the output of the frequency multiplier 20 to the firststage (flipflop 401) of the counter 15. The reason why the feedbackpulses 21 are fed to the pulse counter 15 is to provide a speed feedbackloop. That is to say, it is preferable not to rotate the servo-motor 18too fast. The feedback pluses 21 will subtract from the content of thepulse counter 15 and the speed of the servomotor 18 will thereby bereduced. In this embodiment, the feedback pulses 21 are multiplied fourtimes to stabilize the feedback loop. Also, it should be understood thatthe coefficient of the multiplier is decided only by the stability ofthe speed feedback loop, so the coefficient of the multiplier is notlimited to a factor of four times.

In the above connection, the flip-flops 401 through 404 are utilized tocount up the successive pulse train 172, and the flip-flops 405 and 406are utilized to designate the frequency of sine and cosine waves whichare to control the servo-motor 18. To briefly explain the pulse counter15, the case wherein only add command pulses 173 and the successivepulse train 172 are fed to the pulse counter 15 will be hereinafterdescribed.

Table 2 is provided to explain the pulse counter 15 for the case whereinthe successive pulse train 172 and the add command pulses 173 are fed. ll l l 0 TABLE 2 FF FF FF FF FF FF Content of 401 402 403 404 405 406Pulse Counter 0 o o 0 o 0 0 l 0 0 0 0 O l 0 l 0 0 0 0 2 1 l 0 0 0 0 3 1d 1 1 d i) 15 0 1 1 1 0 0 14 l 1 1 1 0 0 15 0 o o 0 0 l5 1 0 0 0 1 0 140 o 0 0 n l 0 0 0 0 0 1 1 At first, the flip-flops 401 through 406 areall set to 0. Then, the first 15 pulses of the successive pulse train172 are counted up by the flip-flops 401 through 404, and in this case,the AND gates 442 through 425 are opened and the content of the pulsecounter 15 will change from 0 to 15 in decimal code. Then, the next 16pulses of the successive pulse train are counted up by the flip-flops401 through 404 from 0 to 15, but in this case the flip-flop 405 becomes1, and so the AND gates 426 through 429 are opened and the outputs 434through 437 will change from 15 t0 0 in decimal code. It is thus seenthat the content of the pulse counter 15 alternatively changes itscontent from 0 to 15, and then from 15 to 0 in response to the arrivalof the successive pulse train.

The relationship between the outputs 443 through 446 and the flip-flops405 and 406 are shown in FIG. 5. Since the flip-flop 406 changes itsstate every 32 pulses of the successive pulse train 172, the pulseinterval 1- of the output 443 is equal to the time that it takes tocount up the successive pulse train 172 from 0 to 15 and then to countdown to 0. And since, as described before, the number of the successivepulse trains is proportional to the deviation, the pulse interval '1- ofthe output 443 is also proportional to the deviation and is used as thefrequency of the sine wave. The output 444 has a sign opposite to theoutput 443, and the output 445 is A r ahead of the output 443, so theoutput 445 is used as the frequency of the cosine wave. The output 446has a sign opposite to that of the output 445.

FIG. 6 shows a block diagram of the function generator 16 and the poweramplifier 17. The content of the pulse counter 15, or the outputs 434through 437 are fed to a fixed memory 601, and are also fed to a fixedmemory 606 through inverters 602 through 605. The fixed memory 601transforms the content of the pulse counter 15 into a correspondingamplitude for the sine wave. In other words, one-fourth of the sine waveis divided into 16 portions, and the fixed memory 601 memorizes theamplitudes of the sine wave corresponding to the 16 portions. Now, ifthe content of the pulse counter 15 designates a certain portion of thesine wave, then the fixed memory 601 will transform the same into thecorresponding amplitude in binary code, and then transmits it to pulseamplifiers 607 through 610 and then to resistors 611 through 614.

The resistors 611 through 614 are connected to an analogue gate 615, andalso to an analogue gate 617 through an inverter 616. The analogue gates615 and 617 are connected to an operational amplifier 610. The resistors611 through 614 and the operational amplifier 618 operate as a D-Aconverter. The gate signal for the analogue gate 615 is the output 443of the flip-flop 406, and the gate signal for the analogue gate 617 isthe output 444. The resistance of the resistor 614 is two times largerthan that of the resistor 613, which is two times larger than that ofthe resistor 613, which is two times larger than that of the resistor612, which, in turn, is two times larger than the resistance of theresistor 611. Thus, although the output of the fixed memory 601 isdesignated in binary code, it can be converted into an analogue value bythe resistors 611 through 614 and the operational amplifier 616.

As described above in connection with MG. 4, the content of the pulsecounter 15 alternatively changes from 0 to 15 and then from 15 to 0.During the first cycle of the changing of the content from 0 to 15 andthen from 15 to 0, the gate signal 443 is 1, so the analogue gate 615opens, and during the next cycle, the gate signal 444 is 1, so theanalogue gate 617 opens. The output waveforms of the analogue gates 615and 617 are shown in FIG. 7, and the same are added by the operationalamplifier 618 so the output of the operational amplifier 618 becomes thesine wave, whose frequency is proportional to the deviation.

The fixed memory 606 memorizes the amplitudes of onefourth of a cosinewave divided into 16 portions. The other elements connected to the fixedmemory 606 are all the same as those connected to the fixed memory 601.The numerals 607i through 618' correspond to the numerals 607 through618, respectively. The gate signals fed to the analogue gate 615 and 617are the output 445 and 446. Thus, the output of the operationalamplifier 618 is the cosine wave shown in FIG. 7, whose frequency isalso proportional to the deviation.

The sine wave generated in the function generator 16 is fed to the poweramplifier 17. If the output of the amplifier 618 is fed to the excitingwinding 18 of the servo-motor 18, the supplied voltage will be constantin value and variable in frequency. However, since the impedance of thewinding 18 changes in response to frequency, the current flowing throughthe winding 18, will increase as the frequency decreases. Thus, in orderto avoid a burning of the winding, it is necessary to provide means forcontrolling the current therethrough.

The power amplifier 17 comprises an operational amplifier 619, afeedback register 620, and an input impedance which is the parallelconnection of a capacitor 621 and a resistor 622. The frequencycharacteristics of the power amplifier are shown in FIG. 15. In FIG. itis seen that the output voltage E of the power amplifier is nearlyconstant until the frequency increases to a certain value, at which timethe voltage will increase as the frequency increases. Accordingly, asthe impedance of the exciting winding 18 increases as the frequencyincreases, the current flowing through the winding 18 will remain at anearly constant value.

As abovementioned, according to the present invention, the instructionpulses 11 will move the servomotor 18 by an angle of rotationproportional to the number of instruction pulses 11 counted by thedeviation register 12, which deviation is converted to sine and cosinewaves, whose frequency is proportional to the deviation. Thus, the speedcontrol for the servomotor 18 is made by the sine and the cosine waves.The angle of rotation of the servo-motor 18 is detected by the positiondetector 19 and the feedback pulses 21 are fed to the deviation register12. When the deviation becomes 0, the servo-motor will stop, after therotation of a predetermined angle. Therefore, it can be easilyunderstood that the servo-motor 18 can be controlled by the sine and thecosine waves which are generated by a digital operation and whosefrequency is variable.

It should be understood that in the above embodiments, the convertedsine wave is directly amplified. Since power amplifiers are generallynot suitable for amplifying a sine wave, it is more efficient to effectpulse width modulation (PWM) for the sine wave. This enables a poweramplifier to be utilized which is suitable for amplifying pulses.

FIG. 8 is a block diagram of another embodiment of the presentinvention. The deviation register 12, the pulse generator 14, the gatecircuit 13, the pulse counter 15 and the position detector 19 are thesame as those shown in FIG. 1, and accordingly, are not shown in FIG. 8.Furthermore, in FIG. 8, only a sine wave amplifier circuit is shown,because a cosine wave amplifier circuit can be easily obtained once thedetails of the sine wave amplifier circuit are given.

The fixed memory 601 in FIG. 8 is the same as that shown in FIG. 6. Theoutput signals of the fixed memory 601, or the binary codes representingthe amplitude of a sine wave are fed to a register 801. The content ofthe register 801 is fed to a subtract counter 803 through an AND gate802. The reference pulses generated by the pulse generator 14 are alsofed to the AND gate 802 as a gate pulse 804. A clock pulse oscillator805 is provided, and generates clock pulses, whose frequency is nearly2" times as great as that of the pulse generator 14. The n is equal tothe number of bits of the register 801. The content of the subtractcounter 803 is subtracted by the clock pulses, and whenever the subtractcounter 803 becomes 0 the clock pulses will be stopped by any suitablegate means (not shown), and a zero signal 806 will be fed to flip-flops807 and 808 to reset them. The flip-flop 807 is set by the gate signal804.

A memory 809, such as a register, is provided to memorize a constantvalue. The constant value of the memory 809 is coincided with thecontent of the subtract counter 806 by a coincidence circuit 810. Anoutput from the coincidence circuit 810 will set the flipflop 808.

The set output of the flip-flop 807 is fed to an AND gate 811 and alsoto an AND gate 813 through an inverter 824, and to an inverter 815through an OR gate 825. The set output of the flip-flop 808 is fed to anAND gate 812 and also to an AND gate 814 through an inverter 826. Thegate signal 443 shown in FIG. 6 is fed to the AND gates 811 and 814, andthe gate signal 444 is fed to the AND gates 812 and 813. The outputs ofAND gates 811 and 812 are amplified by the pulse amplifier 816 throughan OR gate 817 and are then fed to a power transistor 820, such as ofthe NPN type. The outputs of the AND gates 813 and 814 are amplified bythe pulse amplifier 818 through an OR gate 819 and are then fed to avpower transistor 821, such as of the PNP type. The outputs of theinverter 815 are fed to transistors 822 and 823. The load of thetransistors 820 and 821 is the exciting winding 18,.

The output of the fixed memory 601 or the amplitude at a point on a sinewave represented in binary code is fed to the register 801. The AND gate802 will open for every reference pulse 804, and as such the content ofthe register 801 is shifted to the subtract counter 803. Also, theflip-flop 807 is set by the reference pulse 804. The subtract counter803 counts down the clock pulses from its content and if it becomes 0,the zero signal 806 is transmitted to reset the flip-flop 807, so thatthe width of the output pulse or PWM signal 828 of the flip-flop 807 isdirectly proportional to the content of the fixed memory 601.

FIG. 9 is the time chart to explain the embodiment shown in FIG. 8. InFIG. 9, a situation is shown wherein the content of the fixed memory 601or amplitude of the sine wave changes in response pulse 804. Now atfirst the content of the fixed memory is 7. The reference pulse 804 isfed to the AND gate 802 to shift the content of the register 801 to thereversible counter 803, and is also fed to the flipflop 807 to set it.This is shown in FIG. 9. Then clock pulses are also fed to the counter.803 to be subtracted from the contents thereof-Seven clock pulses aresubtracted, and at last the content of the counter 803 becomes 0, thenthe zero signal 806 resets the flip-flop 807. Therefore, the output 828of the flip-flop 807 becomes as shown in FIG. 9, and the width of theoutput 828 is proportional to 7. When the content of the fixed memory601 becomes 8, the output 828 becomes as shown in FIG. 9, having a pulsewidth proportional to 8. Accordingly, the output 828 designates a PWMsignal into which a sine wave is modulated. It will be readilyunderstood, of course, that FIG. 9 explains the logical operation, whileFIG. 10 shows the whole wave form of the PWM signal generated in thecircuit shown in FIG. 8.

From the operation mentioned above a sine wave is modulated into PWMsignals 828, which are fed to the AND gates 811 and 813. The gatesignals 443 and 444 are also fed to the AND gates 811 and 813,respectively, and the input pulses of the transistors 820 and 821 arethe pulse width modulated sine wave as shown in FIG. 10.

Referring now to FIG. 11, it is seen that each input pulse to thetransistor 820 will turn the same on, and current will flow therethroughand the winding 18, with a certain time constant, and when the inputpulse falls the transistor 820 will turn off. In this manner, the meancurrent flowing through the winding 18, will take a sine wave form.

In this embodiment, the distortion of the sine wave flowing through thewinding 18, must be a minimum. However, pulse amplifying by a powertransistor is considerably difficult, because a power transistor isusually used as a low frequency amplifier. The switching operation of apower transistor is as shown in FIG. 12, and the rise time t, and thefall time t, is decided in accordance with the construction of thetransistor.

In order to eliminate the above defect, one of the transistors 820 and821 is switched on by the PWM signals 828, while the other is switchedon by correction pulses whose width is very narrow, such as having afall time t, whose fall is timed to be equal to that of one of thetransistors, as shown in FIG. 13.

Then, during the overlap time of the PWM signal and the correctionpulse, the current flows through the transistors 820 and 821, and notthrough the winding 18,. In this manner, any distortion by the fall timet, can be effectively reduced.

The correction pulse can be made as follows. In FIG. 8, the memory 809memorizes the constant value which designates the pulse width of thecorrection pulse. Now in this embodiment, the constant value is I. Thecontent of the subtract counter 803 is subtracted, and when it becomes1, the coincidence circuit 810 transmits a coincidence signal to theflip-flop 808 to thereby set the same. As the flip-flop 808 is reset bythe zero signal 806, the output of the flip-flop 808, or the correctionpulse 829 becomes as shown in FIG. 9, having a narrow pulse width whosefall is timed to be equal to that of one of the transistors.

It is easily understood that the time of fall of the correction pulse827 is equal to that of the PWM signal 828. Since the correction pulse827 is fed to the AND gate 812 and the AND gate 814 through the inverter826, and since the gate signal 444 is also fed to the AND gate 814, thesupplied pulse to the transistors 820 and 821 become as shown in FIG.13.

Furthermore, harmonics of the current are also generated when thetransistor 820 or 821 are switched off. Such harmonics are unpreferablein controlling the servo-motor 18. The harmonics are eliminated bymaintaining the current flowing through the winding 18, at a constantvalue, even if a transistor turns off. As described before, the outputof the flip-flop 807 or the PWM signal 828 and the output of theinverter 824 are inverted by the inverter 815 and are fed to thetransistors 822 and 823. Thus, if the transistor 820 turns off, thetransistor 823 will turn on, and the current flowing through the winding18, will be maintained and any harmonics are thereby eliminated. Ofcourse, when the transistor 821 turns off, the transistor 822 turns on.

In the above-described embodiment, the instruction pulses 11 areconverted to the PWM signal 828 modulated by a sine wave or a cosinewave by pulse width and then the PWM signal 828 is remodulated to a sineor a cosine wave to drive the windings. In this manner, the pulses canbe easily amplified and a large power can be obtained.

FIG. 14 shows still one other embodiment of this invention. In thisembodiment, means are provided to make a PWM signal which is modulatedby a sine wave by a pulse width generated by the function generator 16in FIG. 1. The sine wave 1401 or the output of the operational amplifier618 in FIG. 6, and a sawtooth wave 1402 are added by an adder 1403. Theadded signal is fed to a Schmitt circuit 1404 and also to a Schmittcircuit 1405 through an inverter 1406. It can then be easily understoodthat a sine wave is modulated by the pulse width and the outputs of theSchmitt circuit 1404 and 1405 become as shown in FIG. 10. The outputs ofthe Schmitt circuits 1404 and 1405 are amplified by amplifiers 1407 and1408 and then fed to the transistors 820 and 821 in FIG. 8, and thewinding 18, is thereby excited.

In addition, the outputs of the Schmitt circuits 1404 and 1405 are fedto transistors 822 and 823 through an OR gate 1409 and an inverter 1410to eliminate the harmonics thereof. The sawtooth wave 1402 is fed to aSchmitt circuit 1411 to provide the correction pulse 827 shown in FIG.8. In this manner, the output of the Schmitt circuit 1411 is fed to theAND gate 812 and to the AND gate 814 through an inverter 1412.

It should now be apparent, as described above, that in accordance withthe present invention, a digital servo-mechanism is provided in which avariable frequency power supply is provided by a digital operation. Inthis manner, the servo-motor can be controlled by a sine wave ofvariable frequency. Furthermore, a PWM wave of a sine wave can beobtained, and it is possible to employ a large power servo-motor.

Obviously, numerous modifications and variations of the presentinvention are possible in light of the above teachings. It is thereforeto be understood that within the scope of the appended claims theinvention may be practiced otherwise than as specifically describedherein.

What is claimed is:

l. A digital servo-mechanism comprising:

a two-phase servo-motor having an excitation and a control winding,

a position detector for detecting the angular position of saidservo-motor and for generating feedback pulses of a number which isproportional to said angular position,

means for providing instruction pulses for moving said servo-motor byrotating the same through an angle proportional to the number of theinstruction pulses,

a deviation register to count said feedback pulses and said instructionpulses,

a pulse generator for generating reference pulses,

a gate circuit to multiply said reference pulses with the content ofsaid deviation register and to generate a successive pulse train,

a pulse counter for counting said successive pulse train indicative ofthe deviation and to convert the deviation to a given frequency,

a function generator for generating a sine and a cosine wave accordingto said frequency, and

a power amplifier for amplifying said sine and cosine waves and to drivesaid exciting and control windings of said servo-motor.

2. A digital servo-mechanism according to claim 1,

wherein:

said amplifier has frequency characteristics such that the outputvoltage thereof increases as the frequency increases.

3. A digital servo-mechanism according to claim 1,

wherein:

said sine and cosine waves are added with sawtooth waves to providepulse width modulation signals, and

the PWM signals so provided are amplified to drive the windings of saidservo-motor.

4. A digital servo-mechanism comprising:

a two-phase servo-motor having an excitation and a control winding,

a position detector for detecting the angular position of saidservo-motor and for generating feedback pulses of a number which isproportional to said angular position,

means for providing instruction pulses for moving said servo-motor byrotating the same through an angle proportional to the number of theinstruction pulses,

a deviation register to count said feedback pulses and said instructionpulses,

a pulse generator for generating reference pulses,

a gate circuit to multiply said reference pulses with the content ofsaid deviation register and to generate a successive pulse train,

a pulse counter for counting said successive pulse train indicative ofthe deviation and to convert the deviation to a given frequency,

means to generate a PWM signal according to said frequency,

a power amplifier to amplify said PWM signal, and

means to drive said windings of said servo-motor by said PWM signal.

5. A digital servo-mechanism according to claim 4,

wherein said power amplifier comprises:

wherein said power amplifier comprises:

a power transistor to amplify said PWM input signal,

a load to be supplied power,

a transistor connected in parallel to said load, and

means to turn on said transistor by pulses which are provided byinverting said input signal so as to maintain a current flowing throughsaid load even if said power transistor turns off.

7. A digital servo-mechanism according to claim 4,

wherein said means for generating a PWM signal comprises:

a fixed memory to memorize an amplitude of a function,

means to successively readout the content of said fixed memory inaccordance with said reference pulses,

a clock oscillator to generate clock pulses the number of which isnearly 2 times that of the reference pulses wherein n is equal to thebit number of said counter,

a subtraction counter which is fed the readout content of said fixedmemory and which subtracts said clock pulses from its content andtransmits a zero signal when its content becomes 0, and

a flip-flop which is set by said reference pulses and is reset by saidzero signal to generate said PWM signal.

1. A digital servo-mechanism comprising: a two-phase servo-motor havingan excitation and a control winding, a position detector for detectingthe angular position of said servo-motor and for generating feedbackpulses oF a number which is proportional to said angular position, meansfor providing instruction pulses for moving said servomotor by rotatingthe same through an angle proportional to the number of the instructionpulses, a deviation register to count said feedback pulses and saidinstruction pulses, a pulse generator for generating reference pulses, agate circuit to multiply said reference pulses with the content of saiddeviation register and to generate a successive pulse train, a pulsecounter for counting said successive pulse train indicative of thedeviation and to convert the deviation to a given frequency, a functiongenerator for generating a sine and a cosine wave according to saidfrequency, and a power amplifier for amplifying said sine and cosinewaves and to drive said exciting and control windings of saidservomotor.
 2. A digital servo-mechanism according to claim 1, wherein:said amplifier has frequency characteristics such that the outputvoltage thereof increases as the frequency increases.
 3. A digitalservo-mechanism according to claim 1, wherein: said sine and cosinewaves are added with sawtooth waves to provide pulse width modulationsignals, and the PWM signals so provided are amplified to drive thewindings of said servo-motor.
 4. A digital servo-mechanism comprising: atwo-phase servo-motor having an excitation and a control winding, aposition detector for detecting the angular position of said servo-motorand for generating feedback pulses of a number which is proportional tosaid angular position, means for providing instruction pulses for movingsaid servo-motor by rotating the same through an angle proportional tothe number of the instruction pulses, a deviation register to count saidfeedback pulses and said instruction pulses, a pulse generator forgenerating reference pulses, a gate circuit to multiply said referencepulses with the content of said deviation register and to generate asuccessive pulse train, a pulse counter for counting said successivepulse train indicative of the deviation and to convert the deviation toa given frequency, means to generate a PWM signal according to saidfrequency, a power amplifier to amplify said PWM signal, and means todrive said windings of said servo-motor by said PWM signal.
 5. A digitalservo-mechanism according to claim 4, wherein said power amplifiercomprises: a power transistor for amplifying said PWM input signal, aload to be supplied power, a gate connected in parallel to said load,means to provide correction pulses the pulse width of which is nearlyequal to the fall time of said power transistor and whose fall time isequal to that of said input signal, and means to open said gate by saidcorrection pulses so that a current will not flow through said load whensaid correction pulses arrive.
 6. A digital servo-mechanism according toclaim 4, wherein said power amplifier comprises: a power transistor toamplify said PWM input signal, a load to be supplied power, a transistorconnected in parallel to said load, and means to turn on said transistorby pulses which are provided by inverting said input signal so as tomaintain a current flowing through said load even if said powertransistor turns off.
 7. A digital servo-mechanism according to claim 4,wherein said means for generating a PWM signal comprises: a fixed memoryto memorize an amplitude of a function, means to successively readoutthe content of said fixed memory in accordance with said referencepulses, a clock oscillator to generate clock pulses the number of whichis nearly 2n times that of the reference pulses wherein n is equal tothe bit number of said counter, a subtraction counter which is fed thereadout content of said fixed memory and which subtracts said clockpulses from its content and transmits a zero signal When its contentbecomes 0, and a flip-flop which is set by said reference pulses and isreset by said zero signal to generate said PWM signal.